The present disclosure relates to semiconductor device fabrication, and more specifically, to probe pad structures and methods of forming the probe pad structures, including a split probe pad structure with a non-metal region.
Conventional integrated circuit (IC) (i.e., chip) formation generally occurs on the surface of a semiconductor substrate, e.g., silicon wafer. A substrate may include multiple chips physically separated by a kerf region. Each chip on the substrate generally includes at least one bond pad at the chip's perimeter which provides electrical access to the devices of the chip before and after dicing and packaging. After formation of the chips, and before dicing and packaging, each chip is electrically accessed and tested. The testing may be performed, for example, by accessing the semiconductor devices of the chip through bond pads. Using the bond pads to electrically test the chips may result in damage to bond pads which may render the chips inoperable. Therefore, the kerf region on the substrate may include probe pads electrically connected to respective bond pads for electrical access to the chip during testing.
Turning to the figures, FIG. 1 shows a conventional semiconductor substrate 100 including chips, e.g., chip 102, physically separated from one another by kerf region 104. FIG. 1 also shows chip 102 including at least one bond pad 106, and kerf region 104 including at least one probe pad 108. FIG. 2 shows a cross section of the conventional probe pad 108 and bond pad 106 of FIG. 1. Bond pad 106 may be in electrical communication with semiconductor device structures of chip 102 (see FIG. 1) for providing electrical access to the device structures, for example, a transistor 110. As shown in FIG. 2, probe pad 108, located in kerf region 104, may be electrically connected to bond pad 106 of chip 102 (see FIG. 1) by vias 114, 118 and metal wires 112, 116. Probe pad 108 and bond pad 106 may be connected, for example, through an electrical path 136 (in phantom) starting from probe pad 108 through metal wire 112, vias 114, metal wire 116, vias 118, bridging polysilicon region 120 positioned on shallow trench isolation 122 in substrate 124, vias 126, metal wire 128, vias 130, and metal wire 132 to probe pad 108. Using probe pads 108 to electrically test the chips before dicing and packing may mitigate and/or prevent damage to bond pads 106.
Once the chips have been fabricated and tested, the chips may be separated (i.e., diced) by cutting through the kerf region without damaging the semiconductor devices of the chips. One challenge relative to separating chips on a substrate may include metal debris released by cutting through the kerf region, including the probe pads. As shown in FIG. 2, the chips may be separated by cutting through a scribe lane 134 (in phantom) in kerf region 104, and through probe pad 108 including the structures thereunder. For example, where laser ablation is used to create a groove, cut, or scribe the kerf region to separate the chips, the laser ablation may recast metal debris from metal structures located in the kerf region (e.g., probe pad 108 of FIG. 2, and the structure thereunder). The metal debris may settle on the walls of the chips which may, for example, cause slow grow cracks to form and eventually cause delamination in the chip. The metal debris released during separation of the chips may render the chips inoperable.